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july 1 6 , 2014 | d atasheet v3.2 1 ir3550 60a integrated powirs tage ? features ? peak efficiency up to 95 % at 1.2v ? integrated driver, control mosfet, synchronous mosfet and schottky diode ? input voltage (vin) operating range up to 15 v ? out put voltage range from 0.25v to vcc - 2.5v, or to 5.5v if internal current sense amplifier i s not used ? output current capability of 60a dc ? operation up to 1.0mhz ? i ntegrated current sense amplifier ? vcc under voltage lockout ? thermal flag ? body - braking? load transient support ? diode - emulation high efficiency mode ? compatible with 3.3v pwm logic and vcc tolerant ? compliant with intel drmos v4.0 ? pcb footprint c ompatible with ir3551 and ir3553 ? efficient dual sided cooling ? small 6mm x 6 mm x 0.9mm pqfn package ? lead free rohs compliant package applications ? voltage regulators for cpus, gpus, an d ddr memory ar rays ? high current , low profile dc - dc converters basic application figure 1: ir3550 basic application circuit description the ir3550 int egrated powirs tage ? is a synchronous buck gate dr iver co - packed with a control mosfet and a synchronous mosfet wit h integrated schottky diode . it is optimized internally for pcb layout, heat transfer and driver/mosfet timing. custom designed gate driver and mosfet combination enables higher efficiency at lower output voltages required by cutting edge cpu , gpu and ddr memory designs. up to 1.0mhz switching frequency enables high performance transient response, allowing miniaturization of output inductors, as well as input and output capacitors while maintaining industry leading efficiency. the ir3550s superior efficie ncy enables smallest size and lower solution cost. the ir3550 pcb footprint is compati ble with the ir3551 (50a) and the ir3553 ( 40 a). integrated current sense amplifier achieves superior current sense accuracy and signal to noise ratio vs. best - in - class co ntroller based inductor dcr sense methods. the ir3550 incorporates the body - braking? feature which enables reduction of output capacitors . synchronous diode emulation mo de in the ir3550 removes the zero - current detection burden from the pwm controller and increas es system light - load efficiency. the ir3550 is optimized specifically for cpu core power delivery in server applications. the ability to meet the stringent requirements of the server market also makes the ir3550 ideally suited to powering gpu and dd r memory designs and other high current applications . figure 2: typical ir3550 efficiency & power loss (see note 2 on page 8) sw pwm vin pgnd vcc vcc boost vin vout pwm csin + csin - 4 . 5 v to 7 v lgnd iout iout bbrk # bbrk # refin refin 4 . 5 v to 15 v ir 3550 phsflt # phsflt # 75 77 79 81 83 85 87 89 91 93 95 0 5 10 15 20 25 30 35 40 45 50 55 60 output current (a) efficiency (%) 0 2 4 6 8 10 12 14 16 18 20 power loss (w)
july 1 6 , 2014 | d atasheet v3.2 2 ir3550 60a integrated powirs tage ? pinout diagram figure 3: ir3550 pin diagram, top view ordering information package tape & reel qty part number pqfn, 32 lead 6mm x 6mm 3000 ir3550mtrpbf package qty part number pqfn, 32 lead 6mm x 6mm 100 ir3550mpbf typical application diagram figure 4 : application circuit with current sense amplifier s w p w m v i n p g n d g a t e d r i v e r s a n d c u r r e n t s e n s e a m p l i f i e r l g n d v c c p h s f l t # i o u t v c c b o o s t v i n v o u t p w m i o u t p h s f l t # b b r k # b b r k # r e f i n r e f i n c s i n - c s i n + i r 3 5 5 0 4 . 5 v t o 7 v 4 . 5 v t o 1 5 v c 2 1 0 u f x 2 c 5 0 . 2 2 u f c 3 1 u f r 1 1 0 k c 4 0 . 2 2 u f r 2 2 . 4 9 k l 1 1 5 0 n h c 7 4 7 0 u f 3 1 8 - 2 3 2 4 2 5 2 6 2 7 2 9 2 8 3 0 1 2 1 6 , 1 7 6 - 1 5 c 1 0 . 2 2 u f p g n d 4 3 1 t g n d n o c o n n e c t c 8 1 n f c 9 2 2 n f o p t i o n a l f o r d i o d e e m u l a t i o n s e t u p c 6 2 2 u f
july 1 6 , 2014 | d atasheet v3.2 3 ir3550 60a integrated powirs tage ? typ ical application dia gra m (continued) figure 5 : application circuit with out current sense amplifier functional block dia gram figure 6 : ir3550 functional block diagram s w p w m v i n p g n d g a t e d r i v e r s a n d c u r r e n t s e n s e a m p l i f i e r i o u t v c c p h s f l t # v c c b o o s t v i n p w m r e f i n p h s f l t # b b r k # b b r k # c s + l g n d c s i n - c s i n + i r 3 5 5 0 4 . 5 v t o 7 v 4 . 5 v t o 1 5 v c 2 1 0 u f x 2 c 5 0 . 2 2 u f c 3 0 . 2 2 u f r 1 1 0 k c 4 0 . 2 2 u f r 2 2 . 4 9 k l 1 1 5 0 n h 3 1 8 - 2 3 2 4 2 5 2 6 2 7 2 8 3 0 2 9 1 2 1 6 , 1 7 6 - 1 5 c 1 0 . 2 2 u f p g n d 4 3 1 t g n d n o c o n n e c t c s - v o u t c 7 4 7 0 u f c 6 2 2 u f vin sw pwm 6 7 8 9 10 11 12 13 14 15 18 19 20 21 22 23 vin vin vin vin vin sw sw sw sw sw sw sw sw sw 1 31 16 17 csin - pgnd pgnd tgnd 24 boost power - on reset ( por ) , 3 . 3 v reference , and dead - time control 26 iout 30 vcc 3 bbrk # 27 5 32 gatel gatel driver driver 25 phsflt # 2 csin + 28 lgnd 29 refin current sense amplifier mosfet & thermal detection s q r por 3 . 3 v vcc - + 3 . 3 v 4 pgnd 200 k 18 k - + diode emulation comparator ir 3550 offset - + vcc
july 1 6 , 2014 | d atasheet v3.2 4 ir3550 60a integrated powirs tage ? pin descriptions pin # pin name pin description 1 csin - inverting input to the current sense amplifie r. connect to lgnd if the current sense amplifier is not used. 2 csin+ non - inverting input to the current sense amplifier. connect to lgnd if the current sense amplifier is not used. 3 vcc bias voltage for control logic. connect a minimum 1 uf cap between vcc and pgnd ( pin 4 ) if current sense amplifier is used. connect a minimum 0. 22 uf cap between vcc and pgnd ( pin 4 ) if current sense amplifier is not used. 4 , 16, 17 pgnd power ground of mosfet driver and the synchronous mosfet . mosfet driver signal is r eferenced to this pin. 5 , 32 gatel low - side mosfet driver pin s that can be connected to a test point in order to observe the w aveform. 6 C 15 sw switch node of synchronous buck converter. 18 C 23 vin high current input voltage connection. recommend ed operating range is 4.5v to 15v. connect at least two 10uf 1 206 ceramic capacitors and a 0.22 uf 0402 ceramic capacitor. place the capacitors as close as possible to vin pins and pgnd pins (16 - 17). the 0.22 uf 0402 capacitor should be on the same side of t he pcb as the ir3550. 24 boost bootstrap capacitor connection. the bootstrap capacitor provides the charge to turn on the control mosfet. connect a mi nimum 0.22 f c apacitor from boost to sw pin. place the capacitor as close to boost pin as possible and mi nimiz e parasi tic inductance of pcb routing from the capacitor to sw pin. 25 phsflt# open drain output of the phase fault circuits. connect to an external pull - up resistor. output is low when a mosfet fault or over temperature condition is detected. 26 pwm 3.3v logic level tri - state pwm input and 7v tolerant. high turns the control mosfet on, and low turns the synchronous mosfet on . tri - state tur ns both mosfets off in body - braking? mode. in diode emulation mode, tri - state activates internal diode emulation control. see pwm tri - state input s ection for further d etails about the pwm tri - state f unction s . 27 bbrk# 3.3v logic level input and 7v tolerant with internal weak pull - up to 3.3v. logic low disables both mosfets. pull up to vcc directly or by a 4.7 k resistor if body - braking? is not used. the second function of the bbrk# pin is to select diode emulatiom mode. pulling bbrk# low at least 20ns after vcc passes its uvlo threshold selects internal diode emulation control. see body - braking? mode s ection for further details. 28 lgnd signal ground. driver control logic, analog circuits and ic substrate are referenced to this pin. 29 refin reference voltage input from the pwm controller. iout signal is referenced to the voltage on this pin. connect to lgnd if the current sense amplifier is not used. 30 iout current output signal. voltage on this pin is equal to v(refin) + 32.5 * [v(csin+) C v(csin - )]. float this pin if the current sense amplifier is not used. 31 tgnd this pin is connected to inte rnal power and signal ground of the driver . for best performance of the current sense amplifier, tgnd must be electrically isolated from power ground (pgnd) and signal ground (lgnd) in the pcb layout . connect to pgnd if the current sense amplifier is not used.
july 1 6 , 2014 | d atasheet v3.2 5 ir3550 60a integrated powirs tage ? absolute maximum rat ings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those ind icated in the operational sections of the specifications are not implied. pin number pin name v max v min i s ource i sink 1 csin - vcc + 0.3v - 0.3v 1m a 1m a 2 csin+ vcc + 0.3v - 0.3v 1m a 1m a 3 vcc 8v - 0.3v na 5a for 100ns, 200ma dc 4 pgnd 0.3 v - 0.3v 15ma 15ma 5, 32 gatel vcc + 0.3v - 3v for 20ns, - 0.3v dc 1 a for 100ns, 200ma dc 1 a for 100ns, 200ma dc 6 - 15 sw 2 2 5v - 5v for 20ns, - 0.3v dc 6 5a rms , 90a peak 3 0 a rms , 35a peak 16, 17 pgnd na na 30 a rms , 35a peak 65 a rms , 90a peak 18 - 23 vin 2 25 v - 0.3v 5a rms 25a rms , 30a peak 24 boost 1 33 v - 0.3v 1 a for 100ns, 100ma dc 5a for 100ns, 100ma dc 25 phsflt# vcc + 0.3v - 0.3v 1 ma 20 ma 26 pwm vcc + 0.3v - 0.3v 1ma 1 ma 27 bbrk# vcc + 0.3v - 0.3v 1ma 1ma 28 lgnd 0.3v - 0.3v 15ma 15ma 29 refin 3.5v - 0.3v 1ma 1ma 30 iout vcc + 0.3v - 0.3v 5ma 5ma 31 tgnd 0.3 v - 0.3v na na note: 1. maximum boost C sw = 8v . 2 . maximum vin C sw = 25v . 3. all the m aximum voltage ratings are referenced to pgnd (pins 16 and 17) . thermal information thermal resistance , junction to top ( jc _top ) 14.3 c/w thermal resistance , junction to pcb (pin 17) ( j b ) 1.9 c/w thermal resistance ( ja ) 1 20.2 c/w maximum operating junction temperature - 4 0 to 1 50 c maximum storage temperature range - 65c to 150c esd rating hbm class 1b jedec sta ndard msl rating 3 reflow temp erature 26 0c note : 1. thermal resistance ( ja ) is measured with the component mounted on a high effective thermal conductivity test board in free air . refer to international rectifier application note an - 994 for details .
july 1 6 , 2014 | d atasheet v3.2 6 ir3550 60a integrated powirs tage ? electrical specifica tions the electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. typical values represent the median values, which are related to 25c. recommended operatin g conditions for rel iable operation with margin parameter symbol min max unit recommended vin range vin 4.5 15 v recommended vcc range vcc 4.5 7 v recommended refin range refin 0.25 vcc - 2.5 v recommended switching frequency ? sw 200 1000 khz recommended operating junct ion temperature t j - 4 0 125 c e lectrical characteri stics parameter symbol conditions min typ max unit efficiency and maximum current ir3550 peak efficiency note 1 note 2. see figure 2 . 9 4.5 % note 3. see figure 7. 9 3.5 % ir3550 maximum dc cur rent note 1 i dc_max note 2 . 60 a ir3550 maximum peak current note 1 i pk_max note 4. 5ms load pulse width, 10% load duty cycle. 90 a pwm comparator pwm input high threshold v pwm_high pwm tri - state to high 2.5 v pwm input low threshold v pwm_low pwm tri - state to low 0.8 v pwm tri - state float voltage v pwm_tri pwm floating 1.2 1.65 2.1 v hysteresis v pwm_hys act ive to tri - state or tri - state to active , note 1 65 76 100 mv tri - state propagation delay t pwm_delay pwm tri - state to low transitio n to gatel >1v 38 ns pwm tri - state to high transition to gateh >1v 18 ns pwm sink impedance r pwm_sink 3.67 5.1 8.7 0 k pwm source impedance r pwm_source 3.67 5.1 8.7 0 k internal pull up voltage v pwm_pullup vcc > uvlo 3.3 v minimum pulse wi dth t pwm_min note 1 41 58 n s current sense amplifier csin+/ - bias current i csin_bias - 1 00 0 1 00 n a csin+/ - bias current mismatch i csin_biasmm - 50 0 50 na calibrated input offset voltage v csin_of f set self - calibrated offset, 0.5 v v(refin) 2.25 v 450 v
july 1 6 , 2014 | d atasheet v3.2 7 ir3550 60a integrated powirs tage ? parameter symbol conditions min typ max unit gain g cs 0.5v v(refin) 2.25v , - 5mv *v(csin+) C v(csin - )] 25mv, 0c t j 125c 30.0 32.5 35.0 v /v 0.5v v(refin) 2.25v, - 5mv *v(csin+) C v(csin - )] 25mv 30.0 33.0 36.0 v/v 0.8v v(refin) 2.25v, - 10mv *v(csin+ ) C v(csin - )] 25mv 28.0 31.5 35.0 v/v unity gain bandwidth f bw c(iout) = 10pf. measure at iout. note 1 4.8 6.8 8.8 mhz slew rate s r 6 v / s differential input range v d_in 0.8v v(refin) 2.25v, - 10 2 5 m v common mode input range v c_in 0 vcc - 2.5 v output impedance (iout) r cs_out 62 200 iout sink current i cs_ s ink driving external 3 k 0.5 0.8 1.1 ma diode emulation mode comparator input offset voltage v in_offset note 1 - 12 - 3 3 m v leading edge blanking time t blank v(gatel) >1v starts timer 50 150 200 ns negative current time - out t nc_tout pwm = tri - state, v(sw) - 10mv 12 28 46 s digital input C bbrk# input voltage high v bbrk#_ih 2.0 v input voltage low v bbrk#_il 0.8 v internal pull up resistance r b brk#_pullup vcc > uvlo 69 200 338 k internal pull up voltage v bbrk#_pullup vcc > uvlo 3.3 v digital output C phsflt# out put voltage high v phasflt#_oh vcc v out put voltage low v phasflt#_ol 4ma 150 300 mv input current i phasflt#_in v(phsflt#) = 5.5v 0 1 a phase fault detection control mos fet short threshold v cm_short measure from sw to p gnd 3.3 v sync hronous mos fet short threshold v sm_short measure from sw to p gnd 150 200 250 mv sync hronous mos fet open threshold v sm_open measure from sw to p gnd - 250 - 200 - 150 mv propagation delay t prop pwm high to low cycles 15 cycle thermal flag rising threshold t rise phsflt# drives low, note 1 160 c falling threshold t fall note 1 135 c
july 1 6 , 2014 | d atasheet v3.2 8 ir3550 60a integrated powirs tage ? parameter symbol conditions min typ max unit bootstrap diode forward voltage v fwd i(boost) = 3 0ma, vcc =6.8v 360 520 920 m v vcc under voltage lockout start threshold v vcc_start 3.3 3.7 4 .1 v stop threshold v vcc_stop 3.0 3.4 3.8 v hysteresis v vcc_hys 0.2 0.3 0. 4 v general vcc supply current i vcc vcc = 4.5v to 7 v 4 8 12 ma vin sup ply leakage current i vin vin = 20v, 125c, v(pwm) = tri - state 1 a boost supply current i boost 4.75v < v(boost) - v(sw) < 8v 0.5 1.5 3.0 ma refin bias current i refin - 1.5 0 1 a sw floating voltage v sw_float v(pwm) = tri - state 0.2 0. 4 v sw pu ll down resistance r sw_pulldown bbrk# is low or vcc = 0v 18 k notes 1. guaranteed by design but not tested in production 2. v in =12v, v out =1.2v, ? sw = 300khz, l=21 0nh ( 0.2m ), vcc= 6.8v, c in =47uf x 4, c out =47 0 uf x3, 400lfm airflow, no heat sink, 25 c ambient temperature , and 8 - layer pc b of 3.7 (l) x 2.6 (w). pwm controller loss and i nductor loss are not included. 3. v in =12v, v out =1.2v, ? sw = 400khz, l=15 0nh ( 0.2 9 m ), vcc= 7 v, c in =47uf x 4, c out =470uf x3, no airflow, no heat sink, 25c ambient te mperature , and 8 - layer pc b of 3.7 (l) x 2.6 (w). pwm controller loss and i nductor loss are not included. 4. v in =12v, v out =1.2v, ? sw = 400khz, l=21 0nh ( 0.2m , 13mm x 13mm x 8mm), vcc= 6.8v, c in =47uf x 4, c out =470uf x3, no heat sink, 25c ambient temperatu re, 8 - layer pc b of 3.7 (l) x 2.6 (w), 5ms load pulse width, 10% load duty cycle, and ir3550 junction temerature below 1 25c .
july 1 6 , 2014 | d atasheet v3.2 9 ir3550 60a integrated powirs tage ? typical operating ch aracteristics circuit of figure 32 , v in =12v, v out =1.2v, ? sw = 400khz, l=150 nh ( 0.2 9 m ), vcc= 7 v, t ambient = 25c , no heat sink, no air flow, 8 - layer pcb board of 3.7 ( l) x 2.6 ( w) , no pwm controller loss, no inductor loss, unless specified otherwise. figure 7 : typical ir3550 efficiency fig ure 8 : typical ir3550 power loss figure 9 : thermal derating curve , t case < = 125c figure 10 : normalized power loss vs. input voltage figure 11 : normalized power loss vs. output voltage figure 12 : normalized power loss vs. switching frequency 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 0 5 10 15 20 25 30 35 40 45 50 55 output current (a) efficiency (%) 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 35 40 45 50 55 output current (a) power loss (w) 0.85 0.90 0.95 1.00 1.05 1.10 1.15 5 6 7 8 9 10 11 12 13 14 15 input voltage (v) normalized power loss -2.25 -1.50 -0.75 0.00 0.75 1.50 2.25 case temperature adjustment (c) 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 output voltage (v) normalized power loss -2.25 -1.50 -0.75 0.00 0.75 1.50 2.25 3.00 3.75 4.50 5.25 6.00 case temperature adjustment (c) 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 200 300 400 500 600 700 800 900 1000 switching frequency (khz) normalized power loss -2.25 -1.50 -0.75 0.00 0.75 1.50 2.25 3.00 3.75 4.50 5.25 6.00 case temperature adjustment (c)
july 1 6 , 2014 | d atasheet v3.2 10 ir3550 60a integrated powirs tage ? typical operating ch aracteristics (conti nued) circuit of figure 32 , v in =12v, v out =1.2v, ? sw = 400khz, l=150 nh ( 0.2 9 m ), vcc= 7 v, t ambient = 25c , no heat sink, no air flow, 8 - layer pcb board o f 3.7 (l) x 2.6 (w), no pwm controller loss, no inductor loss, unless specified otherwise. figure 13 : normalized power loss vs. vcc voltage figure 14 : power loss vs. output inductor figure 15 : vcc current vs. switching frequency figure 16 : switching waveform , i out = 0a figure 17 : switching waveform , i out = 50a figure 18 : pwm to sw delay s , i out = 10a pwm 2v/div sw 5v/div 40ns/div pwm 5v/div sw 5v/div gatel 10v/div 400ns/div pwm 5v/div sw 5v/ div gatel 10v/div 400ns/div 0 10 20 30 40 50 60 70 80 90 100 200 300 400 500 600 700 800 900 1000 1100 1200 fsw (khz) vcc current (ma) vcc=6.8v vcc=5v 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 5.00 5.25 5.50 5.75 6.00 6.25 6.50 6.75 7.00 vcc voltage (v) normalized power loss -2.25 -1.50 -0.75 0.00 0.75 1.50 2.25 3.00 case temperature adjustment (c) 0.85 0.90 0.95 1.00 1.05 1.10 1.15 120 130 140 150 160 170 180 190 200 210 output inductor (nh) normalized power loss -2.25 -1.50 -0.75 0.00 0.75 1.50 2.25 case temperature adjustment (c)
july 1 6 , 2014 | d atasheet v3.2 11 ir3550 60a integrated powirs tage ? typical operati ng characteristics ( continued) circuit of figure 32 , v in =12v, v out =1.2v, ? sw = 400khz, l=150 nh ( 0.2 9 m ), vcc= 7 v, t ambient = 25c , no heat sink, no air flow, 8 - layer pcb board of 3.7 (l) x 2.6 (w), no pwm controller loss, no inductor loss, unless specifi ed otherwise. figure 19 : body - braking? delays figure 20 : pwm tri - state delay s , i out = 10a figure 21 : pwm tri - state delay s , i out = 10a figure 22 : diode emulation mode , i out = 3 a figure 23 : body - braking? mode , i out = 3 a figure 24 : diode emulation setup through bbrk# capacitor vcc 2v/div bbrk# 1v/div 2ms/div sw 10v/div bbrk# 5v/div gatel 5v/div 40ns/div pwm 5v/div pwm 2v/div sw 5v/div 100ns/div pwm 2v/div sw 5v/div 100ns/div pwm 2v/div sw 5v/div 400ns/div gatel 10v/div pwm 2v/div sw 5v/div 400ns/div gaetl 10v/div
july 1 6 , 2014 | d atasheet v3.2 12 ir3550 60a integrated powirs tage ? typical operating ch aracteristics (conti nued) circuit of figure 32 , v in =12v, v out =1.2v, ? sw = 400khz, l=150 nh ( 0.2 9 m ), vcc= 7 v, t ambient = 25c , no heat sink, no air flow, 8 - layer pcb board of 3.7 (l) x 2.6 (w), no pwm controller loss, no inductor loss, unless specified otherwise. figure 2 5 : diode emulation setup through bbrk# input f igure 2 6 : diode emulation setup through bbrk# input f igure 2 7 : current sense amplifier output vs. current figure 28 : current se nse amplifier output , i out = 0a figure 29 : current sense amplifier output , i out = 2 0a figure 30 : current sense amplifier output, i out = 40a vcc 2v/div bbrk# 2v/div 4ms/div vcc 2v/div bbrk# 2v/div 4ms/div v(iout) - v(refin) 0.2v/div il 10a/div 2us/div sw 20v/div v(iout) - v(refin) 0.2v/d iv il 10a/div 2us/div sw 20v/div v(iout) - v(refin) 0.2v/div il 10a/div 2us/div sw 20v/div 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0 5 10 15 20 25 30 35 40 45 50 output current (a) iout-refin (v)
july 1 6 , 2014 | d atasheet v3.2 13 ir3550 60a integrated powirs tage ? theory of operation description the ir 3550 powirs tage ? is a synchronous buck driver with co - packed mosfets with integrated schottky diode , which provides system designers with ease of use and flexibility require d in cutting edge cpu, gpu and ddr m emory power delivery designs and other high - current low - profile appl ications . the ir 3550 is designed to work with a pwm controller . it incorporates a continuously self - calibrated current sense amp lifier, optimized for use with i nductor dcr sensing. the current sense amplifier provides signal gain and noise immunity, su pplying multi phase systems with a superior design toolbox for programmed impedance designs. the ir3550 provides a phase f ault signal capable of detecting open or shorted mosfets, or an over - temperature condition in the vicinity of the power stage. the ir 3550 accepts an active low body - braking? input which disables both mosfets to enhance transient performance or provide a high impedance output. the ir 3550 provides diode emulation feature which avoids negative current in the synchronous mosfet and improves ligh t load efficiency . the ir 3550 pwm input is compatible with 3.3v logic signal and 7v tolerant. it accepts 3 - level pwm input signals with tri - state. bbrk# pin functions the bbrk# pin has two functions. during nor mal operation, it accepts direct control signal from the pwm controller to enable body - braking?, which turns off both control and synchronous mosfets to improve the load transient response. the second function of bbrk# pin is to select body - braking? (tri - state) or diode emulation mode when pwm pi n recei ves a tri - state signal. the seletion is recongnized right after vcc pas s es its uvlo threshold during the vcc power up. if the bbrk# input is always high, the default operation mode is body - braking?, in which both mosfets will be turned off when the pwm input is in tri - state. if the bbrk# input has been pulled low for at least 20ns after the vcc passes its uvlo threshold during power up , the diode emulation mode is set. pwm input in tri - state will activate a synchronous diode e mulation feature allowi ng designers to maximize system efficiency at light loads without compromising transient performance. once the diode emulation mode is set, it cannot be reset until the vcc power is recycled. pwm tri - state input the ir3550 pwm accepts 3 - level input signals . when pwm input is high, the synchronous mosfet is turned off and the control mosfet is turned on. when pwm input is low, control mosfet is turned off and synchronous mosfet is turned on. figures 16 - 18 show the pwm input and the corresponding s w and gate l output . if pwm pin is floated , the built - in resistors pull the pwm pin into a tri - state region centered around 1.65v. when pwm input voltage is in tri - state region , the ir3550 will go into either body - braking? mode or diode emulation mode depending on bbrk# selection during vcc power up . body - braking? mode international rectifiers body - braking? is a n operation mode in which two mosfets are turned off . when the synchronous mosfet is off, the higher voltage across the shottky diode in parallel helps dis charging the inductor current faster, which reduces the output voltage overshoot. the body - braking? can be used either to enhance transient response of the converter after load release or to provide a high impedance output. there are two ways to place the ir3550 in body - braking? mode , either controlling the bbrk# pin directly or through a pwm tri - state signal. both control signals are usually from the pwm controller. p ulling bbrk# low forces the ir3550 into body - braking? mode rapidly, which is usually used to enhance converter transient response after load release , as shown in figure 19 . releasing bbrk# forces the ir3550 out of body - braking? mode quickly. the bbrk# low turns off both mosfets and therefore can also be used to disable a converter. please no te that soft start may not be available when bbrk# is pulled high to enable the converter. if the bbrk# input is always high, the body - braking? is activated when the pwm input enters the tri - state region , as shown in figure s 20 and 21 . comparing to pulling down the bbrk# pin directly, t he body - braking? response to pwm tri - state signal is slower due to the hold - off time
july 1 6 , 2014 | d atasheet v3.2 14 ir3550 60a integrated powirs tage ? created by the pwm pin para s itic capacitor with the pull - up and pull - down resistor s of pwm pin. for better performance, no more than 100pf p arasitic capacitive load should be present on the pwm line of ir 3550 . synchronous diode em ulation mode an addit ional feature of the ir3550 is the synchronous diode emulation m ode . this function enables increased efficiency by preventing negative inductor current from flowing in the synchronous mosfet. as shown i n figure 22 , w hen the pwm input enters the tri - state region the control mosfet is turned off first, and the synchronous mosfet is initially turned on and then is turned off when the output current reaches zero. if the sensed output current does not reach zero within a set amount of time the gate driver will assume that the output is de - biased and turn off the synchronous mosfet , allowing the switch node to float. this is in contrast to the body - bra king? mode shown in figure 2 3 , where gatel follows pwm input. the schottky diode in parallel with the synchronous mosfet conducts for a longer period of time and therefore lowers the light load efficiency. the zero current det ection circuit in the ir3550 i s independent of the current sense amplifier and therefore still functions even if the current sense amplifier is not used. as shown in figure 6, a n offset is added to the diode emulation comparator so that a slightly positive output current in the induct or and synchronous mosfet is treated as zero current to accommodate propagation delays, preventing any negative current flowing in t he synchronous mosfet. this cause s the schottky diode in parallel with the synchronous mosfet to conduct before th e inductor current actually reaches zero, and the conduction time increases with i nductance of the output inductor. to set the ir3550 in diode emulation mode, the bbrk# p in must be toggled low at least once after the vcc passes its uvlo threshold during power up . on e simple way is to use the internal bbrk# pull - up resistor (200k typical) with an external capacitor from bbrk# pin to lgnd , as shown in figure 4. to ensure the diode emulation mode is properly set, the bbrk# voltage should be lower than 0.8v when the vcc voltage passes its uvlo threshold (3.3v minimum and 3.7v typical), as shown in figure 24 . a digital signal from the pwm controller can also be used to set the diode emulation mode . the bbrk# signal can either be pulled low for at least 2 0ns after the vcc passes its uvlo threshold , as shown in figure 25 , or be pull ed low before vcc power up and then release d after the vcc passes its uvlo threshold, as shown in figure 26 . once the diode emulation mode is set, it cannot be reset until the vcc power is recycl ed. phase fault and ther mal flag output the phase fault circuit looks at the switch node with respect to ground to determine whether there is a defective mos fet in the phase. the output of the phase fault signal is high during normal operation and is pull e d low when there is a fault. each driver monitors the mosfet it drives. if the switch node is les s than a certain voltage above g round when the pwm signal goes low or if the switch n ode is a certain voltage above g round when the pwm sig nal rises, this giv es a fault signal. if there are a number of consecutive faults the phase fault signal is asserted. thermal flag circuit monitors the temperature of the ir 3550 . if the temperature goes above a threshold (16 0c typical) the phsflt# pin is pulled low after a maximum delay of 100us. the phsflt# pin can be pulled low by either the phase fault circuit or the thermal flag circuit , but the ir3550 rel ie s on the system to take protective action s . the phase fault signal could be used by the system to turn off the ac/d c converter or blow a fuse to disconnect the dc/dc converter input from the supply . if phsflt# is not used it can be floated or connected to lgnd . lossless average ind uctor current sensing inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across th e capacitor, as shown in figure 31 . the equation of the current sensing network is as follows. cs cs l l l cs cs l cs c sr r l s r s i c sr s v s v ? ? ? ? ? 1 1 ) ( 1 1 ) ( ) ( l l r s i ) ( ? cs cs l c r r l when ?
july 1 6 , 2014 | d atasheet v3.2 15 ir3550 60a integrated powirs tage ? figure 3 1 : inductor current sensing usually the resistor r cs and capacitor c cs are chosen so that the time constant of r cs and c cs equals the inductor time constant , which is the inductance l over the inductor dcr (r l ). if the two time constants match, the voltage across c cs is proportional to the current through l, and the sense circuit can be treated as if only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component of the inductor current. the advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch current s. the output voltage can be positioned to meet a load line based on real time information. t his is the only sense method that can support a single cycle transient response. other methods provide no information during either load increase (low side sensing ) or load decrease (high side sensing). current sense amplif ier a high speed differential current sense amplifier is located in the ir3550, as shown in figure 6 . its gain is nominally 32.5, and the inductor dcr increase with temperature is not compensated inside the ir3550 . the current sense amplifier output iout is referenced to refin , which is usually connected to a reference voltage fr om the pwm controller. figure 27 shows the differential voltage of v(iout) C v(refin) v ersus the inductor current and re flects the inductor dc r increase with temperature at higher current. the current sense amplifier can accept positive differential input up to 25mv and negative input up to - 10mv before clipping. the output of the current sense amplifier is summed with the reference voltage refin and sent to the iout pin . the refin voltage is to ensure at light loads there is enough output range to accommodate the negative current ripple shown in figure 28. in a multiphase converter, t he iout pins of all the phases can be ti ed together through resistors , and the iout voltage represents the average current through all the inductors and is used by the controller for adaptive voltage positioning. the input offset voltage is the primary source of error for the current signal. in order to obtain very accurate current signal, the current sense amplifier continuously calibrates itself , and the input offset of this amplifier is within +/ - 450uv. this calibration algorithm can create a small ripple on io ut with a frequency of fsw/128. if the ir3550 current sense amplifier is required , connect its output iout and the reference voltage refin to the pwm controller and connect the inductor sense circuit as shown in figure 4. if the current sense amplifier is not needed, tie csin+, csin - a nd refin pins to lgnd and f loat iout pin, as shown in figure 5. maximum output volta ge when the ir3550 current sense amplifier is used, the maximum output voltage is l imited by the vcc voltage used and should be lower than vcc C 2.5v to ensure enough headr oom for the current sense amplifier. the maximum voltage is 4.3v when 6.8v vcc is used , but is only 2.5v when 5v vcc is used . when the ir3550 current sense amplifier is not used, the maximum voltage is not limited by the vcc voltage. the ir3550 can suppor t up to 5.5v output voltage but the output current must be derated since the mosfet ratio was optim ized for duty cycle s of 10% to 20 %. design procedures power loss calculati on the single - phase ir3550 efficiency and power loss measurement circuit is show n in figure 32. the ir3550 power loss is determined by, where both mosfet loss and the driver loss are included, but the pwm controller and the inductor losses are not included. sw vin csin + csin - ir 3550 v in v out cin c cs l cout r cs r l - + i l + v cs - current sense amplifier + v l - out sw vcc cc in in loss i v i v i v p ? ? ? ? ? ?
july 1 6 , 2014 | d atasheet v3.2 16 ir3550 60a integrated powirs tage ? figure 32: ir3550 power loss measurement figure 7 sho ws the measured single - ph ase ir3550 efficiency under the default test conditions, v in =12v, v out =1.2v, ? sw = 400khz, l=150 nh ( 0.2 9 m ), vcc= 7 v, t ambient = 25c , no heat sink, and no air flow. the efficiency of an interleaved multiphase ir3550 converter is always higher than that of a single - phase under the same conditions due to the reduced input rms current and more input/output capa citors. the measured single - phase ir3550 p ower loss under the same conditions is provided in figure 8. if any of the application condition, i.e. input voltage, output voltage, switching frequency, vcc mosfet driver voltage or inductance , is different from those of figure 8, a set of normalized power loss curves should be used . obtain the normalizing factors from figure 10 to figure 14 for the new application conditions; multiply these factors by the power loss obtained from figure 8 for the required load c urrent. as an example, the power loss calculation procedures under different conditions, v in =10v, v out =1v, ? sw = 300khz, vcc= 5v, l=210 nh , vcc= 5v, i out =40a, t ambient = 25c , no heat sink, and no air flow , are as follows. 1) d etermine the power loss at 40a unde r the default test conditions of v in =12 v, v out =1 .2 v, ? sw = 400khz, l=15 0 nh , vcc= 7 v, t ambient = 25c , no heat sink, and no air flow. it is 4.8 w from figure 8. 2) determine the input voltage normalizing factor with v in =10v, which is 0.96 based on the dashed lin es in figure 10. 3) determine the output voltage normalizing factor with v out =1v, which is 0.92 based on the dashed lines in figure 11. 4) determine the switching frequency normalizing factor with ? sw = 300khz, which is 0.98 based on the dashed lines in figure 1 2 . 5) determine the vcc mosfet drive voltage normalizing factor with vcc= 5v, which is 1.16 based on the dashed lines in figure 13 . 6) determine the inductance normalizing factor with l=210 nh , which is 0.95 based on the dashed lines in figure 14. 7) multiply the po wer loss under the default conditions by the five normalizing factors to obtain the power loss under the new conditions , which is 4.8w x 0.9 6 x 0.92 x 0.98 x 1.16 x 0.9 5 = 4. 58 w . thermal derating figure 9 shows the ir3550 thermal derating curve with the ca se temperature controlled at or below 125c. the test conditions are v in =12v, v out =1.2v, ? sw =400khz, l=150 nh ( 0.2 9 m ), vcc= 7 v, t ambient = 0 c to 90 c , with and without heat sink, and a irflow = 0lfm /100lfm /200lfm /4 00lfm. if any of the application condition, i.e. input voltage, output voltage, switching frequency, vcc mosfet driver volta ge, or inductance is different from those of figure 9, a set of ir3550 case temperature adjustment curves should be used. obtain the temperature deltas from figure 10 to figure 14 for the new application conditions; sum these deltas and then subtract from the ir3550 case temperature obt ained from figure 9 for the required load current . 8) from figure 9, determine the maximum current at the required ambient temperature under the default conditions, which is 48a at 45 c with 0lfm airflow and the ir3550 case temperature of 125c. 9) determine th e case temperature with v in =10v, which is - 0. 6 based on the dashed lines in figure 10. 10) determine the case temperature with v out =1v, which is - 1. 2 based on the dashed lines in figure 11. 11) determine the case temperature with ? sw = 300khz , which is - 0. 3 bas ed on the dashed lines in figure 12. s w v i n p g n d v c c b o o s t p w m c s i n + c s i n - l g n d i o u t b b r k # r e f i n i r 3 5 5 0 p h s f l t # v i n v o u t c 2 4 7 u f x 4 c 5 0 . 2 2 u f c 4 0 . 2 2 u f r 2 2 . 4 9 k l 1 1 5 0 n h c 6 4 7 0 u f x 3 c 1 0 . 2 2 u f v c c r 1 1 0 k i v c c i i n i o u t c 3 1 u f c 7 1 n f v s w
july 1 6 , 2014 | d atasheet v3.2 17 ir3550 60a integrated powirs tage ? 12) determine the case temperature with vcc = 5v , which is +2.4 based on the dashed lines in figure 13. 13) determine the case temperature with l=210nh , which is - 0. 8 based on the dashed lines in figure 14. 14) sum the ca se temp erature adjustment from 9) to 13 ), - 0.6 - 1.2 - 0.3 +2.4 - 0.8 = - 0.5 . add the delta to the required ambient te mperature in step 8), 45c + ( - 0.5c) = 44.5c, at which the maximum current is reduced to 4 9 a when the allowed junction temperature is 125 c, as shown in figure 9. if only 105c junction temperature is allowed, the required ambient temperature is equivalent to 44.5c + (125c - 105c) = 64.5 c, which indicates 4 1 a maximum current at the 45c required ambient temperature. inductor current sen sing capacitor c cs and resistor r cs if the ir3550 is used with inductor dcr sensing, care must be taken in the printed circuit board layout to make a kelvin connection across the inductor dcr. the dc resistance of the inductor is utilized to sense the indu ctor current. usually the resistor r cs and capacitor c cs in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage across the capacitor c cs represents the inductor current. measure the inductance l and the inductor dc resistance r l . pre - select the capacitor c cs and calculate r cs as follows. input capacitors c vi n at least two 10uf 1206 ceramic capacitors and one 0.22 uf 0402 ceramic capacitor are recommended for decoupling the vin to p gnd connection . the 0.22 uf 0402 capacitor should be on the same side of the pcb as the ir3550 and next to the vin and pgnd pins. adding additional capacitance and use of capacitors with lower esr and mounted with low inductance routing will improve efficie ncy and reduce overall system noise, especially in single - phase designs or during high current operation . bootstrap capacitor c b oo st a minimum of 0.22 uf 0402 capacitor is required for the b ootstrap circuit. a high temperature 0.22uf or greater value 0402 c apacitor is recommended. it should be mounted on the same side of the pcb as the ir3550 and as close as possible to the b oost p in. a low - inductance pcb routing of the sw pin connection to the other terminal of the b ootstrap capacitor is required to minimi z e the ringing between the boost and sw pins. vcc decoupling c apacitor c vcc a 0.22 uf to 1uf ceramic decoupling capacitor is required at the vcc pin. it should be mounted on the same side of the pcb as the ir3550 and as close as possible to the vcc and pgnd (pin 4 ) . low inductance routing between the vcc capacitor and the ir3550 pins is strongly recommended. body - braking? pin f unction the bbrk# p in should be pulled up to vcc if the feature is not used by the pwm controller. use of a 4.7 k resistor or a direct connection to vcc is recommended. mounting of heat sin ks care should be taken in the mounting of heat sinks so as no t to short - circuit nearby components. the vcc and bootstrap capacitors are typically mounted on the same side of th e pcb as the ir3550 . the mounting height of these capacitors must be considered when selecting their package sizes. high output voltage design considerations the ir3550 is capable of creating output voltages above the 3.3v recommended maximum output voltag e as there are no restrictions inside the ir3550 on the duty cycle applied to the pwm pin. however if the current sense feature is required, the common mode range of the current sense amplifier inputs must be considered. a violation of the current sense in put common mode range may cause unexpected ir3550 behavior. also the output current rating of the device will be reduced as the duty cycle increases. in very high duty cycle applications sufficient time must be provided for replenishment of the bootstrap c apacitor for the control mosfet drive . layout example contact international rectifier for a layout example suitable for your specific application. cs l cs c r l r ?
july 1 6 , 2014 | d atasheet v3.2 18 ir3550 60a integrated powirs tage ? metal and component placement ? lead land width should be equal to nominal part lead width. the minimum lead t o lead spacing should be 0.2mm to prevent shorting. ? lead land length should be equa l to maximum part lead length +0.15 - 0.3 mm outboard extension and 0 to + 0.05mm inboard extension. the outboard extension ensures a large and visible toe fillet, and th e inboard extension will accommodate any part misalignment and ensure a fillet. ? center pad land length and width should be equal to max imum part pad length and width. ? only 0.30mm diameter via shall be placed in the area of the power pad lands and conne cted to power planes to minimize the noise effect on the ic and to improve thermal performance . figure 33 : metal and component placement * contact i nternational r ectifier to receive an electronic pcb library file in cadence allegro or cad dxf/d wg format . 1 2 3 4 5 31 32 6 7 8 9 10 11 12 13 14 15 16 17 18 19 29 28 27 26 25 24 23 22 21 30 20
july 1 6 , 2014 | d atasheet v3.2 19 ir3550 60a integrated powirs tage ? solder resist ? the solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. the solder resist miss - alignment is a maximum of 0.05mm and it is recommended that the low power signal lead lands are all non solder mask defined (nsmd). therefore pulling the s/r 0.06mm will always e nsure nsmd pads. ? the minimum solder resist width is 0.13mm typical . ? at the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solde r resist width of 0.17mm remains. ? the dimensions of power land pad s, vin, pgnd, tgnd and sw, are non solder mask defined ( n smd ). the equivalent pcb layout becomes solder mask defined (smd ) after power shape routing. ? ensure that the solder resist in - betwe en the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land . figure 34 : solder resist * contact i nternational r ectifier to receive a n electronic pcb library file in cadence allegro or cad dxf/dwg format .
july 1 6 , 2014 | d atasheet v3.2 20 ir3550 60a integrated powirs tage ? stencil design ? the stencil apertures for the lead lands should be approximately 65% to 75 % of the area of the lead lands depending on stencil thickness . reducing the amount of solder d eposited will minimize the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. ? t he low power signal stencil lead land apertures should therefore be shortened in length to keep area ratio of 65% to 75% while centered on lead land. ? the power pad s vin, pgnd , tgnd and sw, land pad aperture s should be approximately 65% to 75 % area of sol der on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. solder paste on large pads is broken down into small sections with a minimum gap of 0.2mm between allowing for out - gassing during solder reflow. ? the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste . figure 35 : stencil design * contact i nternational r ectifier to receive an electronic pcb library file in cadence allegro or cad dxf/dwg format .
july 1 6 , 2014 | d atasheet v3.2 21 ir3550 60a integrated powirs tage ? marking information figure 36 : pqfn 6 mm x 6mm package infor mation figure 37 : pqfn 6mm x 6mm 3 5 5 0 m ? y w w ? x x x x s i t e / d a t e / m a r k i n g c o d e l o t c o d e
july 1 6 , 2014 | d atasheet v3.2 22 ir3550 60a integrated powirs tage ? data and specifications subject to change without notice. this product will be designed and qualified for the industrial market. qualification standards can be f ound on irs web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 visit us at www.irf.com for sales contact information . www.irf.com

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